1. Field of the Invention
The present invention is directed generally to converting parallel data to serial, high speed differential signals. More specifically, but without limitation thereto, the present invention is directed to a method of deskewing an internal clock of a data serializer with respect to an external ASIC core.
2. Description of the Prior Art
In integrated circuit design, a transmitter for serializing parallel data is integrated with an Application-Specific Integrated Circuit (ASIC) core design supplied by a customer to an integrated circuit manufacturer. To properly transfer data between the transmitter and the ASIC core, the insertion delay of the clock signal from the ASIC must be matched to the clock signal of the data serializer in the transmitter.
In one aspect of the present invention, an automatic delay matching circuit for a data serializer includes a phase-locked loop for synthesizing a transmitter clock signal for an external circuit, a phase interpolator coupled to the phase-locked loop for delaying or advancing the transmitter clock signal in response to a phase control signal to generate a delayed or advanced transmitter clock signal for the data serializer, a phase detector for measuring a phase difference between the delayed or advanced transmitter clock signal further delayed through the data serializer and the transmitter clock signal delayed through an external circuit, and a loop filter coupled to the phase detector for generating the phase control signal as a function of the phase difference between the delayed or advanced transmitter clock signal further delayed through the data serializer and the transmitter clock signal delayed through the external circuit.
In another aspect of the present invention, a method of delay matching for a data serializer includes steps for synthesizing a transmitter clock signal, delaying or advancing the transmitter clock signal in response to a phase control signal to generate a delayed or advanced transmitter clock signal, measuring a phase difference between the transmitter clock signal delayed through an external circuit and the delayed or advanced transmitter clock signal further delayed through the data serializer, and generating the phase control signal as a function of the phase difference between the delayed or advanced transmitter clock signal further delayed through the data serializer and the transmitter clock signal delayed through the external circuit.